Scenarios are conceivable where a plurality of loads—such as, e.g., light emitting diodes (LEDs)—are placed in an array and circuitry of a device is provided to individually power each one of the loads. This is typically achieved by providing a cell of the device per load where each cell includes a current source to selectively power the associated load. Typically, the current source includes a field-effect transistor (FET) which acts as a switch for selectively powering the respective load.
Sometimes, it is desirable to test operational reliability of the device. One kind of such test is the gate stress test of the FETs. Here, it is desirable to measure leakage currents between a source contact and a drain contact of each one of the FETs before and after applying a stress voltage.
However, such tests may not be possible or only possible to a limited degree when a comparably large number of cells of a device needs to be tested. Individually contacting each cell, e.g., by means of a needle card or the like, may be cumbersome and subject to failure. Further, there may be a limited amount of space available per cell; also, a distance between neighboring cells may be comparably small. All this makes it time consuming and costly to execute a front-end gate stress test. Therefore, testing before final assembly (front-end testing), e.g. by connecting the loads is technically challenging; when a substrate or wafer on which the device is arranged has not been cut to dimensions which allow testing to be executed, this is further complicated. Executing the gate stress test after final assembly (back-end testing) is expensive, as failing current sources cannot be filtered out at an early production stage.